1. Field of the Invention
The present invention relates to an ESD protection device and a layout thereof. More particularly, the present invention relates to an ESD protection device with equal-substrate-potential technology and a layout thereof.
2. Description of Related Art
Electronic products are often impacted by ESD in practical use. Generally speaking, an ESD voltage is much higher than a common supply voltage, and discharge models can be classified into human-body model (HBM), machine model (MM), and charge-device model (CDM) based on different voltage levels generated by ESD. When ESD occurs, the ESD current is likely to burn the elements, such that some ESD protection measures must be taken in the circuit to effectively isolate the ESD current, so as to prevent the elements from being damaged.
Commonly, a design of ESD protection device is disposed between a core circuit and a pad to protect internal circuits. There are several tests for ESD protection devices, which can be classified into PD, PS, ND, and NS modes. The PD/ND mode inputs a positive pulse/negative pulse via the pad to bypass the ESD current to the conducting wire of a system voltage VDD. The PS/NS mode inputs a positive pulse/negative pulse via the pad to bypass the ESD current to the conducting wire of a ground voltage VSS.
FIG. 1 is a block view of an ESD protection circuit. Referring to FIG. 1, the PD mode inputs a positive pulse 105 via a pad 101 and uses an ESD protection device 102 to bypass an ESD current to the system voltage trace VDD, so as to protect a core circuit 104. The NS mode inputs a negative pulse 106 via the pad 101 and uses an ESD protection device 103 to bypass an ESD current to the ground voltage trace VSS, so as to protect the core circuit 104. The operations of the PS, ND modes can be deduced in the same way. Further, electrostatic charges may be accumulated during the operation of the core circuit 104, so the electrostatic charges generated by the core circuit 104 can also be bypassed and discharged by the ESD protection devices 102, 103.
A conventional ESD protection circuit is usually implemented by a gate-grounded n-channel metal-oxide-semiconductor (GGNMOS) transistor. FIG. 2 shows an ESD protection device implemented by a GGNMOS transistor. Referring to FIG. 2, when a core circuit 204 operates normally, as the gate of an NMOS transistor MN1 is grounded, the NMOS transistor MN1 is turned off and will not be conducted. When ESD occurs, a high voltage 205 enters via a pad 201. When the high voltage 205 exceeds a drain/substrate breakdown voltage of the NMOS transistor, the drain/substrate of the NMOS transistor may be broken down and generate a bulk current which triggers parasitic transistors inside the NMOS transistor to bypass the ESD current.
As the ESD protection circuit withstands the high voltage ESD, a channel width of several hundreds of microns is required in the layout. Thus, a layout of multi-finger type is used to reduce the occupied silicon area. However, the above layout manner may result in a different base resistance of a lateral parasitic bipolar junction transistor (BJT) inside each finger of the NMOS transistor, i.e., the parasitic transistor closer to a central circuit has a higher base resistance. When a snapback breakdown of an NMOS transistor occurs, the ESD current may be concentrated and conducted to a ground terminal via the lateral parasitic BJT of the broken-down NMOS transistor. As the NMOS transistor that has been broken down lowers the potential of the conducting wire coupled thereto, the ESD pulse will not trigger other NMOS transistors, thus causing a non-uniform problem of bypassing the ESD current and weakening the ESD protection ability. In order to solve the above problems, the base resistances of the parasitic transistors must be substantially the same.
FIG. 3A is a top view of an ESD protection circuit layout according to U.S. Pat. No. 5,811,856. FIG. 3B is a sectional view of the ESD protection circuit layout according to the U.S. Pat. No. 5,811,856. Referring to FIGS. 3A and 3B, the ESD protection circuit can be regarded as the ESD protection device 103 in FIG. 1. The guard-ring formed by a P+ doped region 301 is used to avoid ESD current drain. A gate 302 and N+ doped regions 303, 304 form a GGNMOS transistor, and the N+ doped regions 303, 304 and a substrate 308 form a parasitic transistor 309. N+ doped regions 307, 311, and the substrate 308 form a parasitic transistor 312. Moreover, the N+ doped regions 305, 307 and the substrate 308 form a parasitic transistor 310.
A method of solving the non-uniform problem of bypassing the ESD current involves embedding a grounded P+ diffusion region 306 into the source 304 of a neighboring NMOS transistor, and making the base resistances of the parasitic transistors 309, 310, 312 being substantially the same, so as to simultaneously trigger the parasitic transistors to bypass the ESD current. However, the layout of embedding the P+ diffusion region 306 not only increases the layout area, but also results in an over low substrate resistance of the NMOS transistor in a deep-submicron complementary metal-oxide-semiconductor (CMOS) transistor process, thus making it difficult to trigger the internal parasitic transistors and bypass the ESD current in time to protect the core circuit.
FIG. 4 shows an ESD protection circuit disclosed in “Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-um Salicided CMOS process” (Proc. IEEE Int. Symp. Electronics, Circuits and Systems, 2001, pp. 361-364) published by Mr. M.-D. Ker, C.-H. Chuang, and W.-Y. Lo. Referring to FIG. 4, another method of solving the non-uniform problem of bypassing the ESD current involves coupling a sensing circuit to the gate of an MOS transistor. The sensing circuit is generally constituted by a resistor RP1 (or RN1) and a capacitor CP1 (or CN1). When the sensing circuit senses the occurrence of an ESD event, the sensing circuit provides a bias to the gates of MOS transistors MP1, MP2 (or MN1, MN2), so as to simultaneously turn on the transistors MP1, MP2 (or MN1, MN2) to bypass the ESD current. The PMOS transistors MP1, MP2, capacitor CP1, and resistor RP1 can be regarded as internal elements of the ESD protection device 102 in FIG. 1. The NMOS transistors MN1, MN2, capacitor CN1, and resistor RN1 can be regarded as internal elements of the ESD protection device 103 in FIG. 1. The resistors RN1, RP1 and capacitors CN1, CP1 can be adjusted to provide a bias to the gates of the NMOS transistors MN1, MN2 and PMOS transistors MP1, MP2 to reduce the trigger voltage of the NMOS transistors MN1, MN2 and PMOS transistors MP1, MP2. Thus, when ESD occurs, a smaller trigger voltage can trigger the NMOS transistors MN1, MN2 or PMOS transistors MP1, MP2 in time to bypass the ESD current. However, the high bias applied on the gate of the NMOS transistor MN1/PMOS transistor MP1 may generate a larger channel current, and a higher electric field may cause the breakdown of a thin gate-oxide layer, thus weakening the ESD protection ability. In addition, the impedance of the resistors RN1, RP1 in a common sensing circuit is extremely high (approximately 100 kilo-ohm), which may also increase the layout area.
FIG. 5 shows an ESD protection circuit according to the U.S. Pat. No. 5,631,793. Referring to FIG. 5, the NMOS transistors MN1, resistor RN1, and capacitor CN1 are internal elements of the ESD protection device 103 in FIG. 1. A method of solving the non-uniform problem of bypassing the ESD current involves electrically connecting a sensing circuit to the substrate of the GGNMOS transistors MN1, MN2. The sensing circuit is constituted by a resistor RN1 and a capacitor CN1. The resistor RN1 and the capacitor CN1 can be adjusted to provide an appropriate voltage to the bodies of the parasitic transistors (i.e., the substrates of the GGNMOS transistors MN1, MN2), so as to increase the base voltage of the parasitic transistors, i.e., reducing the trigger voltage of the GGNMOS transistors MN1, MN2, such that the internal parasitic transistors can be triggered simultaneously to solve the non-uniform problem of bypassing the ESD current. Therefore, it is not necessary to apply a bias to the gates of the NMOS transistors MN1, MN2, thus avoiding generating an extra channel current that weakens the ESD protection ability. However, the additional resistor RN1 and capacitor CN1 may also increase the layout area.
FIG. 6 shows an ESD protection circuit according to the U.S. Pat. No. 5,686,751. Referring to FIG. 6, a technology of solving the non-uniform problem of bypassing the ESD current involves triggering each finger of the NMOS transistor in a domino manner. In FIG. 6, Rd1-Rdi are respectively ballast resistors of the drains of NMOS transistors MN1-MNi, and Rs1-Rsi are respectively ballast resistors of the sources of the NMOS transistors MN1-MNi. The NMOS transistors MN1-MNi and resistors Rd1-Rdi, Rs1-Rsi are internal elements of the ESD protection device 103 in FIG. 1. When ESD occurs, as long as one of the NMOS transistors (for example, the NMOS transistor MN1) is triggered, the ESD current provides a voltage to the gate of the NMOS transistor MN2 via the ballast resistor Rs1. The triggered NMOS transistor MN2 then allows the ESD current to pass through the ballast resistor Rs2 to provide a voltage to the gate of the NMOS transistor MN3. The NMOS transistors MN3-MNi are triggered in the same way. However, though the non-uniform problem of bypassing the ESD current can be solved by the above conventional art, the complexity of the layout is increased.